Traditional integrated circuit behavioral models, such as those based on the I/O buffer information specification (IBIS), describe electrical characteristics of inputs and outputs of a device without disclosing proprietary information. Typically, behavioral models are used for signal integrity analysis on a system level. However, these traditional behavioral models are not delay models for timing purposes, and thus, the syntax of these models fails to capture timing characteristics of the devices, such as power-induced jitter effects for I/O buffers. As a result, these traditional behavioral models often lead to inaccurate circuit analysis for current high-speed designs.